Invention Grant
- Patent Title: Three-dimensional chip-to-wafer integration
- Patent Title (中): 三维芯片到晶片集成
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Application No.: US13281534Application Date: 2011-10-26
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Publication No.: US09190391B2Publication Date: 2015-11-17
- Inventor: Amit Subhash Kelkar , Karthik Thambidurai , Viren Khandekar , Hien D. Nguyen
- Applicant: Amit Subhash Kelkar , Karthik Thambidurai , Viren Khandekar , Hien D. Nguyen
- Applicant Address: US CA San Jose
- Assignee: Maxim Integrated Products, Inc.
- Current Assignee: Maxim Integrated Products, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Advent, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L25/065 ; H01L23/00 ; H01L23/538 ; H01L23/31 ; H01L21/56 ; H01L25/00
Abstract:
An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.
Public/Granted literature
- US20130105966A1 THREE-DIMENSIONAL CHIP-TO-WAFER INTEGRATION Public/Granted day:2013-05-02
Information query
IPC分类:
