Invention Grant
- Patent Title: Three-dimensional stacked structured ASIC devices and methods of fabrication thereof
- Patent Title (中): 三维堆叠结构化ASIC器件及其制造方法
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Application No.: US14283101Application Date: 2014-05-20
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Publication No.: US09190392B1Publication Date: 2015-11-17
- Inventor: Subhash L. Shinde , John Teifel , Richard S. Flores , Robert L. Jarecki, Jr. , Todd Bauer
- Applicant: Sandia Corporation
- Applicant Address: US NM Albuquerque
- Assignee: Sandia Corporation
- Current Assignee: Sandia Corporation
- Current Assignee Address: US NM Albuquerque
- Agent Martin I. Finston
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/065 ; H01L23/538 ; H01L23/00 ; H01L27/02 ; H01L27/06
Abstract:
A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.
Information query
IPC分类:
