Invention Grant
US09190418B2 Junction butting in SOI transistor with embedded source/drain
有权
具有嵌入式源极/漏极的SOI晶体管中的结对接
- Patent Title: Junction butting in SOI transistor with embedded source/drain
- Patent Title (中): 具有嵌入式源极/漏极的SOI晶体管中的结对接
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Application No.: US14217572Application Date: 2014-03-18
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Publication No.: US09190418B2Publication Date: 2015-11-17
- Inventor: Anthony I. Chou , Murshed M. Chowdhury , Arvind Kumar , Robert R. Robison
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Hopewell Junction
- Assignee: GLOBALFOUNDRIES U.S. 2 LLC
- Current Assignee: GLOBALFOUNDRIES U.S. 2 LLC
- Current Assignee Address: US NY Hopewell Junction
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L27/12 ; H01L29/66 ; H01L21/84 ; H01L21/324 ; H01L21/225 ; H01L21/265 ; H01L29/167

Abstract:
After forming source/drain trenches within a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, portions of the trenches adjacent channel regions of a semiconductor structure are covered either by sacrificial spacers formed on sidewalls of the trenches or by photoresist layer portions. The sacrificial spacers or photoresist layer portions shield portions of the top semiconductor layer underneath the trenches from subsequent ion implantation for forming junction butting. The ion implantation regions thus are confined only in un-shielded, sublayered portions of the top semiconductor layer that are away from the channel regions of the semiconductor structure. The width of the ion implantation regions are controlled such that the implanted dopants do not diffuse into the channel regions during subsequent thermal cycles so as to suppress the short channel effects.
Public/Granted literature
- US20150270284A1 JUNCTION BUTTING IN SOI TRANSISTOR WITH EMBEDDED SOURCE/DRAIN Public/Granted day:2015-09-24
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