The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. A highly localized ion implantation is used to set the threshold voltage of the transistor and to improve the short channel behavior of the final device. Based on high-K metal gate technology, this transistor has reduced threshold uncertainty and superior source and drain conductance.