Invention Grant
- Patent Title: Power semiconductor module having pattern laminated region
- Patent Title (中): 功率半导体模块具有图案层叠区域
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Application No.: US14409301Application Date: 2013-07-17
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Publication No.: US09196604B2Publication Date: 2015-11-24
- Inventor: Yoshiko Tamada , Seiji Oka
- Applicant: Mitsubishi Electric Corporation
- Applicant Address: JP Chiyoda-ku
- Assignee: Mitsubishi Electric Corporation
- Current Assignee: Mitsubishi Electric Corporation
- Current Assignee Address: JP Chiyoda-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2012-160113 20120719
- International Application: PCT/JP2013/069380 WO 20130717
- International Announcement: WO2014/014012 WO 20140123
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L25/07 ; H01L23/049 ; H01L23/24 ; H01L23/373 ; H01L23/433 ; H01L23/498 ; H01L23/31 ; H01L25/18 ; H01L23/14 ; H01L23/15 ; H01L23/367 ; H01L23/00 ; H05K1/05 ; H05K3/28

Abstract:
A power semiconductor module includes a base plate as a metallic heat dissipating body, a first insulating layer on the base plate, and a first wiring pattern on the first insulating layer. On a predetermined region that is a part of the first wiring pattern, a second wiring pattern for a second layer is laminated via only a second insulating layer made of resin, thereby forming a pattern laminated region. A power semiconductor element is mounted in a region other than the pattern laminated region on the first wiring pattern. The base plate, the first insulating layer, the first wiring pattern, the second insulating layer, the second wiring pattern, and the power semiconductor element are integrally sealed with a transfer mold resin, thus obtaining the power semiconductor module.
Public/Granted literature
- US20150115288A1 POWER SEMICONDUCTOR MODULE Public/Granted day:2015-04-30
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