Invention Grant
- Patent Title: Method of manufacturing a misfet on an SOI substrate
- Patent Title (中): 在SOI衬底上制造误差的方法
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Application No.: US14579242Application Date: 2014-12-22
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Publication No.: US09196705B2Publication Date: 2015-11-24
- Inventor: Yoshiki Yamamoto , Hideki Makiyama , Toshiaki Iwamatsu , Takaaki Tsunomura
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Miles & Stockbridge P.C.
- Priority: JP2012-011213 20120123; JP2012-163907 20120724
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/66 ; H01L29/786 ; H01L27/12 ; H01L29/417 ; H01L29/423 ; H01L29/78 ; H01L21/768 ; H01L29/08 ; H01L21/265

Abstract:
Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
Public/Granted literature
- US20150111348A1 Semiconductor Device and Manufacturing Method of the Same Public/Granted day:2015-04-23
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