Invention Grant
- Patent Title: Method for manufacturing P-type MOSFET
- Patent Title (中): 制造P型MOSFET的方法
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Application No.: US14004802Application Date: 2012-12-07
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Publication No.: US09196706B2Publication Date: 2015-11-24
- Inventor: Qiuxia Xu , Huilong Zhu , Tianchun Ye , Huajie Zhou , Gaobo Xu , Qingqing Liang
- Applicant: Institute of Microelectronics, Chinese Academy of Sciences
- Applicant Address: CN Beijing
- Assignee: Institute of Microelectronics, Chinese Academy of Sciences
- Current Assignee: Institute of Microelectronics, Chinese Academy of Sciences
- Current Assignee Address: CN Beijing
- Agency: Kinney & Lange, P.A.
- Priority: CN201210506496 20121130
- International Application: PCT/CN2012/086172 WO 20121207
- International Announcement: WO2014/082341 WO 20140605
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8234 ; H01L29/66 ; H01L21/265 ; H01L21/28 ; H01L29/49 ; H01L29/51 ; H01L21/02 ; H01L29/423

Abstract:
Provided is a method for manufacturing a p-type MOSFET, including: forming a part of the MOSFET on a semiconductor substrate including source/drain regions, a replacement gate, and a gate spacer; removing the replacement gate stack of the MOSFET to form a gate opening; forming an interface oxide layer on the exposed surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interface oxide layer; forming a first metal gate layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.
Public/Granted literature
- US20150295067A1 METHOD FOR MANUFACTURING P-TYPE MOSFET Public/Granted day:2015-10-15
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