An error correction code decoder, including a computational memory array having at least a variable node section, a check node section, and a plurality of computational memory cells, each cell capable of storing at least one bit of memory and of performing operations at least on the bit and each cell implementing one node. A controller instructs the computational memory to perform the operations and to write the results of computations on a block of variable nodes into associated set of blocks of check nodes and to write the results of computations on a block of check nodes into associated set of blocks of variable nodes.