Invention Grant
- Patent Title: Lower power assembler
- Patent Title (中): 低功率组装
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Application No.: US11568714Application Date: 2005-05-09
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Publication No.: US09201657B2Publication Date: 2015-12-01
- Inventor: Jeroen Anton Johan Leijten
- Applicant: Jeroen Anton Johan Leijten
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Leydig, Voit & Mayer, Ltd.
- Priority: EP04102104 20040513
- International Application: PCT/IB2005/051491 WO 20050509
- International Announcement: WO2005/111792 WO 20051124
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30 ; G06F9/45

Abstract:
A method for processing data using a time-stationary multiple-instruction word processing apparatus, arranged to execute a plurality of instructions in parallel, said method comprising the following steps: generating a set of multiple-instruction words (INS(i), INS(i+1), INS(i+2)), wherein each multiple-instruction word comprises a plurality of instruction fields, wherein each instruction field encodes control information for a corresponding resource of the processing apparatus, and wherein bit changes between an instruction field related to a no-operation instruction, and a corresponding instruction field of an adjacent multiple-instruction word are minimised; storing input data in a register file (RF0, RF1); processing data retrieved from the register file based on control information derived from the set of multiple-instruction words; disabling the write back of result data to the register file during execution of a no-operation instruction using a first dedicated no-operation code (ws00, ws10, wp00, wp10).
Public/Granted literature
- US20100153691A1 LOWER POWER ASSEMBLER Public/Granted day:2010-06-17
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