A semiconductor memory device according to an embodiment comprises: a plurality of memory cells; a word line; a plurality of first bit lines and a plurality of second bit lines; and a control circuit. The control circuit is capable of executing: a determining operation that determines whether the memory cell which is to be a write-target includes an erase-target cell whose threshold voltage is to be the erase state, or not; and an inverting operation that inverts selection or unselection of the bit line connected to one of the two memory cells adjacent to the erase-target cell, in the first write operation and the second write operation.