Invention Grant
- Patent Title: Memory device having a stacked variable resistance layer
- Patent Title (中): 具有堆叠的可变电阻层的存储器件
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Application No.: US14446419Application Date: 2014-07-30
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Publication No.: US09202845B2Publication Date: 2015-12-01
- Inventor: Masumi Saitoh , Takayuki Ishikawa , Shosuke Fujii , Hidenori Miyagawa , Chika Tanaka , Ichiro Mizushima
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2013-192386 20130917
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24

Abstract:
A memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode.
Public/Granted literature
- US20150076439A1 MEMORY DEVICE Public/Granted day:2015-03-19
Information query
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