Invention Grant
- Patent Title: Method for manufacturing semiconductor structure
- Patent Title (中): 半导体结构的制造方法
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Application No.: US13133120Application Date: 2011-02-25
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Publication No.: US09202913B2Publication Date: 2015-12-01
- Inventor: Huilong Zhu
- Applicant: Huilong Zhu
- Applicant Address: CN Beijing
- Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
- Current Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
- Current Assignee Address: CN Beijing
- Agency: Troutman Sanders LLP
- Priority: CN201010501712 20100930
- International Application: PCT/CN2011/071309 WO 20110225
- International Announcement: WO2012/041037 WO 20120405
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/78 ; H01L29/66

Abstract:
The present application discloses a method for manufacturing a semiconductor structure, comprising the steps of: a) providing a p-type field effect transistor; b) forming a tensile-stressed layer on the p-type field effect transistor; c) removing a portion of the tensile-stressed layer, so that the remaining portion of the tensile-stressed layer generates compressive stress in the channel of the p-type field effect transistor; and d) performing annealing, so as to achieve the object of memorizing compressive stress in a channel of a transistor and improving the performance of the transistor. The method according to the present invention memorizes the compressive stress in the channel of the transistor by a stress memorization technique, increases mobility of holes, and improves overall performance of the semiconductor structure.
Public/Granted literature
- US20120083106A1 METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE Public/Granted day:2012-04-05
Information query
IPC分类: