A delay line circuit comprises a plurality of delay units configured to receive an input signal and modify the input signal to produce a first output signal. The delay line circuit also comprises a variable delay line unit that comprises an input end configured to receive the first output signal; an output end configured to output a second output signal; a first line between the input end and the output end, the first line comprising, in series, a first inverter, a second inverter, a first speed control unit, and a third inverter; a second line between the input end and the output end, the second line comprising, in series, a fourth inverter, a second speed control unit, a fifth inverter, and a sixth inverter. The delay line circuit is also configured to selectively transmit the received first output signal through one of the first line or the second line.