Disclosed is a wafer-level stacked chip assembly, comprising a plurality of chip layers vertically stacked together with vertically electrical interconnections between the adjacent chip layers realized by TSVs (Through Silicon Via). Each chip layer includes a switching mechanism for selectively bypassing chip coding sequence to deactivate failed IC area and its chip coding sequence, thereby the interconnection relationship among the chip layers can be re-defined and the function and chip code of the failed IC area can be deactivated. Accordingly, any known failed chip in the wafer-level stacking chip assembly can be controlled as a dummy chip to realize the wafer-level chip stacking of non-known good dices with exclusion of failed chip(s).