Invention Grant
US09204538B2 Method of fine line space resolution lithography for integrated circuit features using double patterning technology
有权
使用双重图案化技术的集成电路特征的细线空间分辨率光刻方法
- Patent Title: Method of fine line space resolution lithography for integrated circuit features using double patterning technology
- Patent Title (中): 使用双重图案化技术的集成电路特征的细线空间分辨率光刻方法
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Application No.: US13968804Application Date: 2013-08-16
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Publication No.: US09204538B2Publication Date: 2015-12-01
- Inventor: Chia-Ying Lee , Jyu-Horng Shieh
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H05K1/02 ; H05K3/00 ; H01L21/033 ; H01L21/308 ; H01L21/311
Abstract:
A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill an entirety of the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. The hard mask is etched to remove a portion of the hard mask and to form a second opening, wherein the second opening is between the two parallel portions of the first opening. The second opening is spaced apart from the two parallel portions of the first opening by the spacers. The first opening and the second opening are then extended down into the base material.
Public/Granted literature
- US20150047891A1 Integrated Circuit Features with Fine Line Space and Methods for Forming the Same Public/Granted day:2015-02-19
Information query
