Invention Grant
- Patent Title: Bitline leakage detection in memories
- Patent Title (中): 存储器中的位线泄漏检测
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Application No.: US12608101Application Date: 2009-10-29
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Publication No.: US09208902B2Publication Date: 2015-12-08
- Inventor: Beena Pious , Xiaowei Deng , Wah Kit Loh , Jon Lescrenier
- Applicant: Beena Pious , Xiaowei Deng , Wah Kit Loh , Jon Lescrenier
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Rose Alyssa Keagy; Frank D. Cimino
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G11C29/12 ; G11C29/02 ; G11C11/22 ; G11C11/41 ; G11C29/50
Abstract:
An integrated circuit containing a memory and a sense amplifier. The integrated circuit also containing an extended delay circuit which extends the delay between when a precharged bitline is floated and when a wordline is enabled. A method of testing an integrated circuit to identify bitlines with excessive leakage.
Public/Granted literature
- US20100110807A1 Bitline Leakage Detection in Memories Public/Granted day:2010-05-06
Information query
