Invention Grant
US09209069B2 Method of manufacturing high resistivity SOI substrate with reduced interface conductivity
有权
具有降低的界面电导率的制造高电阻率SOI衬底的方法
- Patent Title: Method of manufacturing high resistivity SOI substrate with reduced interface conductivity
- Patent Title (中): 具有降低的界面电导率的制造高电阻率SOI衬底的方法
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Application No.: US14510929Application Date: 2014-10-09
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Publication No.: US09209069B2Publication Date: 2015-12-08
- Inventor: Jeffrey L. Libbert , Shilpi Vaypayee
- Applicant: SunEdison Semiconductor Limited (UEN201334164H)
- Applicant Address: SG Singapore
- Assignee: SunEdison Semiconductor Limited (UEN201334164H)
- Current Assignee: SunEdison Semiconductor Limited (UEN201334164H)
- Current Assignee Address: SG Singapore
- Agency: Armstrong Teasdale LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/762
Abstract:
A method of preparing a high resistivity single crystal semiconductor handle wafer comprising implanting He ions through a front surface of the high resistivity single crystal semiconductor handle wafer, which is followed by an anneal sufficient to form a nanocavity layer in the damage region formed by He ion implantation. The anneal may be prior to or concurrent with thermal oxidation to prepare a front oxidized surface layer.
Public/Granted literature
- US20150104926A1 METHOD OF MANUFACTURING HIGH RESISTIVITY SOI SUBSTRATE WITH REDUCED INTERFACE CONDUCITIVITY Public/Granted day:2015-04-16
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