Invention Grant
- Patent Title: Three dimensional integrated circuits stacking approach
- Patent Title (中): 三维集成电路堆叠方式
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Application No.: US13630149Application Date: 2012-09-28
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Publication No.: US09209156B2Publication Date: 2015-12-08
- Inventor: Jing-Cheng Len , Shang-Yun Hou
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/00 ; H01L25/065 ; H01L23/31 ; H01L21/56 ; H01L21/683
Abstract:
A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die(s) bonded to the interposer die can have edge(s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die.
Public/Granted literature
- US20140091473A1 NOVEL THREE DIMENSIONAL INTEGRATED CIRCUITS STACKING APPROACH Public/Granted day:2014-04-03
Information query
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