Invention Grant
- Patent Title: Method for top-side cooled semiconductor package with stacked interconnection plates
- Patent Title (中): 具有堆叠互连板的顶侧冷却半导体封装的方法
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Application No.: US14173151Application Date: 2014-02-05
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Publication No.: US09218987B2Publication Date: 2015-12-22
- Inventor: Kai Liu , François Hébert , Lei Shi
- Applicant: Alpha and Omega Semiconductor Incorporated
- Applicant Address: US CA Sunnyvale
- Assignee: ALPHA AND OMEGA SEMICONDUCTER INCORPORATED
- Current Assignee: ALPHA AND OMEGA SEMICONDUCTER INCORPORATED
- Current Assignee Address: US CA Sunnyvale
- Agent Chein-Hwa S. Tsao; Chen-Chi Lin
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/495 ; H01L23/00 ; H01L21/50

Abstract:
A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.
Public/Granted literature
- US20140154843A1 Method for Top-side Cooled Semiconductor Package with Stacked Interconnection Plates Public/Granted day:2014-06-05
Information query
IPC分类: