A semiconductor wafer has an integrated through substrate via created from a backside of the semiconductor wafer. The semiconductor wafer includes a semiconductor substrate and a shallow trench isolation (STI) layer pad on a surface of the semiconductor substrate. The semiconductor wafer also includes an inter-layer dielectric (ILD) layer formed on a contact etch stop layer, separating the ILD layer from the STI layer pad on the surface of the semiconductor substrate. The semiconductor wafer further includes a through substrate via that extends through the STI layer pad and the semiconductor substrate to couple with at least one contact within the ILD layer. The through substrate via includes a conductive filler material and a sidewall isolation liner layer. The sidewall isolation liner layer has a portion that possibly extends into, but not through, the STI layer pad.