Invention Grant
- Patent Title: 3-D memory arrays
- Patent Title (中): 3-D存储器阵列
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Application No.: US13759627Application Date: 2013-02-05
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Publication No.: US09219070B2Publication Date: 2015-12-22
- Inventor: Deepak Thimmegowda , Brian Cleereman , Khaled Hasnat
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: H01L29/41
- IPC: H01L29/41 ; H01L29/417 ; H01L27/115 ; H01L27/02 ; H01L29/788 ; H01L29/792

Abstract:
A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed.
Public/Granted literature
- US20140217488A1 3-D Memory Arrays Public/Granted day:2014-08-07
Information query
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