DAC includes a decoder that receives N number of reference voltages and an n-bit digital signal (n 4) to select first to third voltages, and an operational amplifier to output (first voltage+second voltage+2 third voltage)/4 voltage. The operational amplifier is able to output, for respective 2^n combinations of the n-bit digital signal, voltage levels from an Ath level, as a base level, to an (A−1+2^n)th level. The N number of reference voltages include Ath level, (A+4)th level, (A−4+2^n) and (A+2^n), and an at most {−4+2^(n−2)} reference voltages obtained by decimating a pre-set at least one reference voltage from {−3+2^(n−2)} reference voltages that are other than the four number of reference voltages from the {1+2^(n−2)} reference voltages corresponding to the voltage levels spaced each other at an interval of 4 levels from the Ath level. N is not less than 4 and not more than 2^(n−2).