Invention Grant
US09224436B2 Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods
有权
装置包括具有单独的全局读写线和/或读出放大器区列选择线和相关方法的存储器阵列
- Patent Title: Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods
- Patent Title (中): 装置包括具有单独的全局读写线和/或读出放大器区列选择线和相关方法的存储器阵列
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Application No.: US13902591Application Date: 2013-05-24
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Publication No.: US09224436B2Publication Date: 2015-12-29
- Inventor: Harish N. Venkata , John F. Schreck , Mansour Fardad
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C7/18
- IPC: G11C7/18 ; G11C7/12 ; G11C7/06

Abstract:
Apparatuses and methods for memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.
Public/Granted literature
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