Invention Grant
- Patent Title: Temperature-based adaptive erase or program parallelism
- Patent Title (中): 基于温度的自适应擦除或程序并行
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Application No.: US13787799Application Date: 2013-03-06
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Publication No.: US09224478B2Publication Date: 2015-12-29
- Inventor: Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
- Applicant: Richard K. Eguchi , Jon S. Choy , Chen He , Kelly K. Taylor
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C16/10 ; G11C7/04 ; G11C16/14 ; G11C16/30 ; G11C16/34

Abstract:
A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.
Public/Granted literature
- US20140254285A1 Temperature-Based Adaptive Erase or Program Parallelism Public/Granted day:2014-09-11
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