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US09224637B1 Bi-level dry etching scheme for transistor contacts 有权
晶体管触点的双层干蚀刻方案

Bi-level dry etching scheme for transistor contacts
Abstract:
Contact holes of different depths for source, drain, and gate connections are formed by common etch steps using a relatively low etch rate material over the gate electrode and a relatively high etch rate material over the source and drain terminals to provide similar etch times for all three holes so that risk of over-etching is reduced.
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