Invention Grant
US09224642B2 Conductive via structures for routing porosity and low via resistance, and processes of making
有权
用于布线孔隙度和低通孔电阻的导电通孔结构以及制造工艺
- Patent Title: Conductive via structures for routing porosity and low via resistance, and processes of making
- Patent Title (中): 用于布线孔隙度和低通孔电阻的导电通孔结构以及制造工艺
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Application No.: US14328979Application Date: 2014-07-11
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Publication No.: US09224642B2Publication Date: 2015-12-29
- Inventor: Hugh Thomas Mair
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frank D. Cimino
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768 ; H01L23/522 ; H01L23/528 ; H01L21/78
Abstract:
An integrated circuit structure includes a first conductive layer (MET4) including a first forked conductive structure (310), an insulating layer (320, ILD45) substantially disposed over the first forked conductive structure (310), a plurality of conductive vias (331-334) through the insulating layer (ILD45) and electrically connecting with the first forked conductive structure (310), and a second conductive layer (MET5) including a second forked conductive structure (340) substantially disposed over at least a portion of the insulating layer (ILD45) and generally perpendicular to the first forked conductive structure (310), the plurality of conductive vias (331-334) electrically connecting with the second forked conductive structure (340). Other structures, devices, and processes are also disclosed.
Public/Granted literature
- US20140322867A1 CONDUCTIVE VIA STRUCTURES FOR ROUTING POROSITY AND LOW VIA RESISTANCE, AND PROCESSES OF MAKING Public/Granted day:2014-10-30
Information query
IPC分类:
