Invention Grant
US09224674B2 Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages
有权
封装的半导体芯片,具有无冲击积层(BBUL)封装的无冲击模封装接口
- Patent Title: Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages
- Patent Title (中): 封装的半导体芯片,具有无冲击积层(BBUL)封装的无冲击模封装接口
-
Application No.: US13996495Application Date: 2011-12-15
-
Publication No.: US09224674B2Publication Date: 2015-12-29
- Inventor: Pramod Malatkar , Weng Hong Teh , John S. Guzek , Robert L. Sankman
- Applicant: Pramod Malatkar , Weng Hong Teh , John S. Guzek , Robert L. Sankman
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2011/065269 WO 20111215
- International Announcement: WO2013/089754 WO 20130620
- Main IPC: H01L27/08
- IPC: H01L27/08 ; H01L23/552 ; H01L23/48 ; H01L23/00

Abstract:
A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.
Public/Granted literature
Information query
IPC分类: