In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and the heavily doped feed guiding region (28, 28A), an improved potential profile is achieved in the drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.