Invention Grant
US09225504B2 Circuit and method for clock data recovery and circuit and method for analyzing equalized signal 有权
用于时钟数据恢复的电路和方法,用于分析均衡信号的电路和方法

Circuit and method for clock data recovery and circuit and method for analyzing equalized signal
Abstract:
A clock data recovery method samples an input signal according to a reference clock to generate a plurality of sampling results. A first and a second sampling clocks are generated according to the reference clock. A phase difference between the two sampling clocks is larger than zero and less than half an UI and each UI corresponds to an input data. Successive UIs of the input signal are sampled according to the first and the second sampling clocks to generate a first and a second sampling results in each UI. The two sampling results are compared to generate a comparison result. An adjusting signal is generated according to the comparison result and the input data. The first and the second sampling clocks are adjusted according to the adjusting signal such that the sampling results of each UI substantially correspond to a peak value at the UI of the input signal.
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