Invention Grant
- Patent Title: IC die top, bottom signals, tap lock, test, scan circuitry
- Patent Title (中): IC芯片顶部，底部信号，抽头锁定，测试，扫描电路
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Application No.: US14816220Application Date: 2015-08-03
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Publication No.: US09229056B2Publication Date: 2016-01-05
- Inventor: Lee D. Whetsel
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Frank D. Cimino
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/3185 ; G01R31/28 ; G01R31/3183
Abstract:
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.
Public/Granted literature
- US20150338463A1 3D TAP AND SCAN PORT ARCHITECTURES Public/Granted day:2015-11-26
Information query
