Invention Grant
- Patent Title: Method for integrated circuit patterning
- Patent Title (中): 集成电路图案化方法
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Application No.: US14212708Application Date: 2014-03-14
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Publication No.: US09229326B2Publication Date: 2016-01-05
- Inventor: Yen-Cheng Lu , Shu-Hao Chang , Shinn-Sheng Yu , Jui-Ching Wu , Jeng-Horng Chen , Anthony Yen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G03F7/20
- IPC: G03F7/20 ; H01L21/311 ; H01L21/268

Abstract:
Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.
Public/Granted literature
- US20150262836A1 Method for Integrated Circuit Patterning Public/Granted day:2015-09-17
Information query
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