Invention Grant
- Patent Title: Self-aligned double patterning
- Patent Title (中): 自对准双重图案化
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Application No.: US14056522Application Date: 2013-10-17
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Publication No.: US09230809B2Publication Date: 2016-01-05
- Inventor: Yu-Sheng Chang , Chung-Ju Lee , Tien-I Bao
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/331
- IPC: H01L21/331 ; H01L21/22 ; H01L21/38 ; H01L21/44 ; H01L21/302 ; H01L21/033 ; H01L21/768 ; H01L21/027 ; H01L21/311
Abstract:
A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer. A thin spacer layer is used to form spacers alongside a pattern. A reverse image of the spacer pattern is formed and an enlargement process is used to slightly widen the pattern. The widened pattern is subsequently used to pattern an underlying layer. This process may be used to form a pattern in a dielectric layer, which openings may then be filled with a conductive material.
Public/Granted literature
- US20150111380A1 Self-aligned Double Patterning Public/Granted day:2015-04-23
Information query
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