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US09231079B1 Stress memorization techniques for transistor devices 有权
晶体管器件的应力记忆技术

Stress memorization techniques for transistor devices
Abstract:
One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.
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