Invention Grant
- Patent Title: Stress memorization techniques for transistor devices
- Patent Title (中): 晶体管器件的应力记忆技术
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Application No.: US14304017Application Date: 2014-06-13
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Publication No.: US09231079B1Publication Date: 2016-01-05
- Inventor: Johannes M. van Meer , Cuiqin Xu , Isabelle Ferain
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/66 ; H01L29/78 ; H01L21/324 ; H01L21/266

Abstract:
One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.
Public/Granted literature
- US20150364570A1 STRESS MEMORIZATION TECHNIQUES FOR TRANSISTOR DEVICES Public/Granted day:2015-12-17
Information query
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