Invention Grant
US09231105B2 Semiconductor device with group-III nitride compound semiconductor layer on substrate for transistor
有权
用于晶体管的衬底上具有III族氮化物化合物半导体层的半导体器件
- Patent Title: Semiconductor device with group-III nitride compound semiconductor layer on substrate for transistor
- Patent Title (中): 用于晶体管的衬底上具有III族氮化物化合物半导体层的半导体器件
-
Application No.: US14464912Application Date: 2014-08-21
-
Publication No.: US09231105B2Publication Date: 2016-01-05
- Inventor: Ippei Kume , Hiroshi Takeda , Toshiharu Nagumo , Takashi Hase
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Miles & Stockbridge P.C.
- Priority: JP2013-175991 20130827
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/20 ; H01L29/40
Abstract:
To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.
Public/Granted literature
- US20150060875A1 SEMICONDUCTOR DEVICE Public/Granted day:2015-03-05
Information query
IPC分类:
