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US09231592B1 Method for synchronizing a multiplicity of clock generating circuits 有权
用于同步多个时钟发生电路的方法

Method for synchronizing a multiplicity of clock generating circuits
Abstract:
A clock generating circuit includes oscillators each having a delay rise vote input, a delay fall vote input, a delay rise output, a delay fall output, and a clock output; a vote rise circuit having inputs coupled individually to the delay rise outputs of the oscillators, and an output coupled in common to the delay rise vote inputs of the oscillators; a vote fall circuit having inputs coupled individually to the delay fall outputs of the oscillators, and an output coupled in common to the delay fall vote inputs of the oscillators; and a vote clock circuit having inputs coupled individually to the clock outputs of the oscillators, and an output for providing a synchronized clock signal.
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