Disclosed is a method for implementing task-process-table based hardware control, which includes dividing a task that has to be implemented by a hardware circuit into multiple sub-processes, and determining the depth of the task process table according to the number of the sub-processes; according to the control information of the hardware unit corresponding to each sub-process and the number (SPAN) of clock cycles occupied by hardware processing for the sub-process, determining the bit width of the task process table and generating the task process table; starting the hardware unit corresponding to each sub-process in an order of the sub-processes, under the control of the control information in the task process table, and completing the processing of each sub-process. A device for implementing hardware control is also disclosed. The disclosure enables precise control of the hardware control flow and is of versatility. For the hardware implementation of a task with a complex algorithm flow, the data processing flow is accurate, and the development efficiency is improved.