Invention Grant
US09244798B1 Programmable micro-core processors for packet parsing with packet ordering
有权
可编程微核处理器,用于使用数据包排序进行数据包解析
- Patent Title: Programmable micro-core processors for packet parsing with packet ordering
- Patent Title (中): 可编程微核处理器,用于使用数据包排序进行数据包解析
-
Application No.: US13164533Application Date: 2011-06-20
-
Publication No.: US09244798B1Publication Date: 2016-01-26
- Inventor: Kaushik Kuila , David T. Hass
- Applicant: Kaushik Kuila , David T. Hass
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox PLLC
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F11/30 ; G06F3/038

Abstract:
Disclosed is an approach for implementing a flexible parser for a networking system. A micro-core parser is implemented to process packets in a networking system. The micro-cores of the parser read the packet headers, and perform any suitably programmed tasks upon those packets and packet headers. One or more caches may be associated with the micro-cores to hold the packet headers. A dependency list is used to maintain proper ordering of packets being processed by the micro-cores.
Information query