Invention Grant
US09244798B1 Programmable micro-core processors for packet parsing with packet ordering 有权
可编程微核处理器,用于使用数据包排序进行数据包解析

Programmable micro-core processors for packet parsing with packet ordering
Abstract:
Disclosed is an approach for implementing a flexible parser for a networking system. A micro-core parser is implemented to process packets in a networking system. The micro-cores of the parser read the packet headers, and perform any suitably programmed tasks upon those packets and packet headers. One or more caches may be associated with the micro-cores to hold the packet headers. A dependency list is used to maintain proper ordering of packets being processed by the micro-cores.
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