Invention Grant
US09244853B2 Tunable multi-tiered STT-MRAM cache for multi-core processors
有权
可调多层STT-MRAM缓存，用于多核处理器
- Patent Title: Tunable multi-tiered STT-MRAM cache for multi-core processors
- Patent Title (中): 可调多层STT-MRAM缓存，用于多核处理器
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Application No.: US13571426Application Date: 2012-08-10
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Publication No.: US09244853B2Publication Date: 2016-01-26
- Inventor: Seung H. Kang , Xiaochun Zhu , Xiaoxia Wu
- Applicant: Seung H. Kang , Xiaochun Zhu , Xiaoxia Wu
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Donaki D. Min; Paul Holdaway
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/08 ; G06F15/78
Abstract:
A multi-core processor is presented. The multi-core processor includes a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache associated with a first core of the multi-core processor and tuned according to first attributes and a second STT-MRAM cache associated with a second core of the multi-core processor and tuned according to second attributes.
Public/Granted literature
- US20140047184A1 TUNABLE MULTI-TIERED STT-MRAM CACHE FOR MULTI-CORE PROCESSORS Public/Granted day:2014-02-13
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