Invention Grant
- Patent Title: Techniques for electromigration stress mitigation in interconnects of an integrated circuit design
- Patent Title (中): 集成电路设计互连中电迁移应力缓解技术
-
Application No.: US14266499Application Date: 2014-04-30
-
Publication No.: US09245086B2Publication Date: 2016-01-26
- Inventor: Ertugrul Demircan , Mehul D. Shroff
- Applicant: Ertugrul Demircan , Mehul D. Shroff
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Agency: Yudell Isidore PLLC
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A technique for electromigration stress mitigation in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph, which represents an interconnect network of an integrated circuit design. A first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress are located. A maximum first stress between the first and second points is determined. In response to determining the maximum first stress between the first and second points is greater than a critical stress, a stub is added to the spanning tree at a node between the first and second points. The maximum first stress between the first and second points is re-determined subsequent to adding the stub.
Public/Granted literature
- US20150046893A1 TECHNIQUES FOR ELECTROMIGRATION STRESS MITIGATION IN INTERCONNECTS OF AN INTEGRATED CIRCUIT DESIGN Public/Granted day:2015-02-12
Information query