Invention Grant
US09245086B2 Techniques for electromigration stress mitigation in interconnects of an integrated circuit design 有权
集成电路设计互连中电迁移应力缓解技术

Techniques for electromigration stress mitigation in interconnects of an integrated circuit design
Abstract:
A technique for electromigration stress mitigation in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph, which represents an interconnect network of an integrated circuit design. A first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress are located. A maximum first stress between the first and second points is determined. In response to determining the maximum first stress between the first and second points is greater than a critical stress, a stub is added to the spanning tree at a node between the first and second points. The maximum first stress between the first and second points is re-determined subsequent to adding the stub.
Information query
Patent Agency Ranking
0/0