Invention Grant
- Patent Title: Method for forming wiring
- Patent Title (中): 布线方法
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Application No.: US14433061Application Date: 2013-08-20
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Publication No.: US09245789B2Publication Date: 2016-01-26
- Inventor: Koichiro Okamoto , Munehiro Tada , Hiromitsu Hada , Toshitsugu Sakamoto
- Applicant: NEC CORPORATION
- Applicant Address: JP Tokyo
- Assignee: NEC CORPORATION
- Current Assignee: NEC CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2012-224323 20121009
- International Application: PCT/JP2013/072640 WO 20130820
- International Announcement: WO2014/057734 WO 20140417
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/768 ; H01L21/311 ; H01L45/00 ; H01L21/02

Abstract:
The present invention addresses the problem of inhibiting the evolution of a poisoning gas to eliminate wiring-pattern resolution failures and thereby forming a desired wiring layer structure to provide functional elements having an improved property yield. This method for forming multi-layered copper interconnect on a semiconductor substrate comprises: forming a multilayer resist structure to form a given resist pattern on a substrate including an interlayer dielectric film that has via holes which have been formed in part thereof and filled with an SOC layer, the multilayer resist structure comprising an SOC layer, an SOG layer, an SiO2 layer, and a chemical amplification type resist superposed in this order from the substrate side; conducting etching using the resist pattern as a mask to form a pattern for a wiring layer and via plugs; and forming the wiring layer and the via plugs in the pattern.
Public/Granted literature
- US20150262864A1 METHOD FOR FORMING WIRING Public/Granted day:2015-09-17
Information query
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