Invention Grant
- Patent Title: Methods of fabricating interconnection structures
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Application No.: US14925821Application Date: 2015-10-28
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Publication No.: US09245796B1Publication Date: 2016-01-26
- Inventor: Keun Do Ban , Cheol Kyu Bok , Min Ae Yoo , Jong Cheon Park
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2014-0115388 20140901
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768
Abstract:
A method of fabricating an interconnection structure according to an embodiment of the present invention, includes patterning a dielectric layer to form a first recession region, including a first nest-shaped recession region having a first width and a first line-shaped recession region having a second width, which is less than the first width. A guide spacer layer is formed on sidewalls of the first recession region to provide a second recession region including a second nest-shaped recession region in the first nest-shaped recession region. A self-assembling block copolymer material is formed to fill the second nest-shaped recession region. The self-assembling block copolymer material is annealed to form a polymer block domain and a polymer block matrix, surrounding the polymer block domain. The polymer block domain is removed to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is etched to form a via cavity.
Information query
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