Invention Grant
US09245898B2 NAND flash memory integrated circuits and processes with controlled gate height
有权
NAND闪存集成电路和具有受控栅极高度的工艺
- Patent Title: NAND flash memory integrated circuits and processes with controlled gate height
- Patent Title (中): NAND闪存集成电路和具有受控栅极高度的工艺
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Application No.: US14320103Application Date: 2014-06-30
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Publication No.: US09245898B2Publication Date: 2016-01-26
- Inventor: Eiichi Fujikura , Susumu Okazaki , Takuya Futase , Fumiaki Toyama , Hiroaki Koketsu
- Applicant: SanDisk Technologies Inc.
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies Inc.
- Current Assignee: SanDisk Technologies Inc.
- Current Assignee Address: US TX Plano
- Agency: Davis Wright Tremaine LLP
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L27/115 ; H01L21/28 ; H01L21/3205 ; H01L21/3213
Abstract:
A NAND flash memory integrated circuit chip includes a cell area and a peripheral area with structures of different heights, with higher structures in the peripheral area to provide low resistance and lower structures in the memory array so that the risk of word line collapse is maintained at acceptable levels.
Public/Granted literature
- US20150380420A1 NAND Flash Memory Integrated Circuits and Processes with Controlled Gate Height Public/Granted day:2015-12-31
Information query
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