Invention Grant
- Patent Title: Vertical double-diffusion MOS and manufacturing technique for the same
- Patent Title (中): 垂直双扩散MOS及其制造技术相同
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Application No.: US14184277Application Date: 2014-02-19
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Publication No.: US09245977B2Publication Date: 2016-01-26
- Inventor: Zhongping Liao
- Applicant: Silergy Semiconductor Technology (Hangzhou) LTD
- Applicant Address: CN Hangzhou
- Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
- Current Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
- Current Assignee Address: CN Hangzhou
- Agent Michael C. Stephens, Jr.
- Priority: CN201310092218 20130321
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/08

Abstract:
In one embodiment, a method of making a VDMOS transistor can include: (i) etching an oxide layer formed on a surface of an epitaxial structure to define an active region of the VDMOS; (ii) injecting and diffusing a first dopant into the active region to form a doping region; (iii) forming a gate oxide layer on the active region; (iv) depositing polysilicon on the gate oxide layer, and etching the polysilicon to form a gate; (v) injecting a second dopant at an end of the gate to form a source, where the first and second dopants have opposite types; (vi) forming a contact hole adjacent to the gate, and injecting a third dopant into the contact hole, where the first and third dopants have a same type; (vii) depositing and etching aluminum on a chip surface; and (viii) coating the aluminum and chip surface with a passivation layer.
Public/Granted literature
- US20140284703A1 VERTICAL DOUBLE-DIFFUSION MOS AND MANUFACTURING TECHNIQUE FOR THE SAME Public/Granted day:2014-09-25
Information query
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