Invention Grant
US09246347B2 Battery charging circuit with serial connection of MOSFET and an enhancement mode JFET configured as reverse blocking diode with low forward voltage drop
有权
具有串联连接MOSFET的电池充电电路和增强型JFET配置为具有低正向压降的反向阻塞二极管
- Patent Title: Battery charging circuit with serial connection of MOSFET and an enhancement mode JFET configured as reverse blocking diode with low forward voltage drop
- Patent Title (中): 具有串联连接MOSFET的电池充电电路和增强型JFET配置为具有低正向压降的反向阻塞二极管
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Application No.: US14101529Application Date: 2013-12-10
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Publication No.: US09246347B2Publication Date: 2016-01-26
- Inventor: Sik Lui , Wei Wang
- Applicant: Sik Lui , Wei Wang
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee Address: US CA Sunnyvale
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H02J7/00 ; H01L27/06
Abstract:
A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode.
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