Invention Grant
US09246928B2 Compiling pattern contexts to scan lanes under instruction execution constraints
有权
编译模式上下文以在指令执行约束下扫描通道
- Patent Title: Compiling pattern contexts to scan lanes under instruction execution constraints
- Patent Title (中): 编译模式上下文以在指令执行约束下扫描通道
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Application No.: US13098772Application Date: 2011-05-02
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Publication No.: US09246928B2Publication Date: 2016-01-26
- Inventor: Kubilay Atasu , Florian Dorfler , Christoph Hagleitner , Jan Van Lunteren
- Applicant: Kubilay Atasu , Florian Dorfler , Christoph Hagleitner , Jan Van Lunteren
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Daniel Morris
- Main IPC: G06F11/00
- IPC: G06F11/00 ; H04L29/06
Abstract:
A technique for determining scan lanes is provided. For a set of patterns, a number of scan lanes is estimated to be utilized on an accelerator. The number of the scan lanes estimated for the set of patterns is iteratively incremented to optimize a throughput of the accelerator. The set of patterns is distributed to the number of the scan lanes as a distribution, and each one of the scan lanes has a predetermined number of engines. A size of a memory space is evaluated that is needed for the distribution to distribute the set of patterns onto the number of scan lanes.
Public/Granted literature
- US20120284222A1 COMPILING PATTERN CONTEXTS TO SCAN LANES UNDER INSTRUCTION EXECUTION CONSTRAINTS Public/Granted day:2012-11-08
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