Invention Grant
US09250288B2 Wafer-level testing method for singulated 3D-stacked chip cubes
有权
用于单片3D堆叠芯片立方体的晶圆级测试方法
- Patent Title: Wafer-level testing method for singulated 3D-stacked chip cubes
- Patent Title (中): 用于单片3D堆叠芯片立方体的晶圆级测试方法
-
Application No.: US14018697Application Date: 2013-09-05
-
Publication No.: US09250288B2Publication Date: 2016-02-02
- Inventor: Kun-Chih Chan , Shin-Kung Chen , Sheng-Chi Lin
- Applicant: POWERTECH TECHNOLOGY INC.
- Applicant Address: TW Hsinchu
- Assignee: POWERTECH TECHNOLOGY INC.
- Current Assignee: POWERTECH TECHNOLOGY INC.
- Current Assignee Address: TW Hsinchu
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
Disclosed is a wafer level testing method for testing a plurality of singulated 3D-stacked chip cubes by utilizing adjustable wafer maps to adjust the pick-and-place positions of the cubes on a carrier wafer. The wafer maps have a plurality of probe-card activated regions each including a plurality of component-attaching regions. Two wafer-level testing steps are performed on the cubes disposed on the carrier wafer according to the wafer maps. By analyzing the electrical testing results of the trial-run wafer-level testing step from the original wafer map, some prone-to-overkill component-attaching regions are confirmed and to create a corrected wafer map which the prone-to-overkill component-attaching regions are excluded from probe-card activated regions. Then, according to the corrected wafer map, cubes are disposed on the carrier wafer without disposing in the prone-to-overkill component-attaching regions. Accordingly, the real-production wafer-level testing step can be run smoothly without unnecessary shut down of adjustment or repair leading to the maximum productivity without overkill issues.
Public/Granted literature
- US20150061718A1 WAFER-LEVEL TESTING METHOD FOR SINGULATED 3D-STACKED CHIP CUBES Public/Granted day:2015-03-05
Information query