Invention Grant
- Patent Title: Multi-processor bus and cache interconnection system
- Patent Title (中): 多处理器总线和缓存互连系统
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Application No.: US14318211Application Date: 2014-06-27
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Publication No.: US09250908B2Publication Date: 2016-02-02
- Inventor: Martin Vorbach , Volker Baumgarte , Frank May , Armin Nuckel
- Applicant: PACT XPP TECHNOLOGIES AG
- Applicant Address: DE Munich
- Assignee: PACT XPP TECHNOLOGIES AG
- Current Assignee: PACT XPP TECHNOLOGIES AG
- Current Assignee Address: DE Munich
- Agent Edward P. Heller, III
- Priority: DE10110530 20010305; DE10111014 20010307; WOPCT/EP01/06703 20010613; DE10129237 20010620; EP1115021 20010620; DE10135210 20010724; DE10135211 20010724; WOPCT/EP01/08534 20010724; DE10139170 20010816; DE10142231 20010829; DE10142894 20010903; DE10142903 20010903; DE10142904 20010903; DE10144732 20010911; DE10144733 20010911; DE10145792 20010917; DE10145795 20010917; DE10146132 20010919; WOPCT/EP01/11299 20010930; WOPCT/EP01/11593 20011008; DE10154259 20011105; DE10154260 20011105; EP1129923 20011214; EP2001331 20020118; DE10202044 20020119; DE10202175 20020120; DE10206653 20020215; DE10206856 20020218; DE10206857 20020218; DE10207224 20020221; DE10207225 20020221; DE10207226 20020221; DE10208434 20020227; DE10208435 20020227
- Main IPC: G06F13/28
- IPC: G06F13/28 ; G06F9/345 ; G06F13/38 ; G06F12/08 ; G06F13/16 ; G06F12/06
Abstract:
A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method.
Public/Granted literature
- US20140310466A1 Multi-processor bus and cache interconnection system Public/Granted day:2014-10-16
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