In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.