Invention Grant
US09251000B2 Apparatuses and methods for combining error coding and modulation schemes
有权
用于组合错误编码和调制方案的装置和方法
- Patent Title: Apparatuses and methods for combining error coding and modulation schemes
- Patent Title (中): 用于组合错误编码和调制方案的装置和方法
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Application No.: US14525602Application Date: 2014-10-28
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Publication No.: US09251000B2Publication Date: 2016-02-02
- Inventor: Chandra C. Varanasi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H03M13/03
- IPC: H03M13/03 ; G06F11/10 ; H03M13/25 ; H03M13/00 ; H03M13/11 ; H03M13/41
Abstract:
Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a Viterbi algorithm and a linear error correcting code decoder.
Public/Granted literature
- US20150074498A1 APPARATUSES AND METHODS FOR COMBINING ERROR CODING AND MODULATION SCHEMES Public/Granted day:2015-03-12
Information query
IPC分类:
