Invention Grant
US09251054B2 Implementing enhanced reliability of systems utilizing dual port DRAM 有权
实现利用双端口DRAM的系统的增强的可靠性

Implementing enhanced reliability of systems utilizing dual port DRAM
Abstract:
A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.
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