Invention Grant
US09251054B2 Implementing enhanced reliability of systems utilizing dual port DRAM
有权
实现利用双端口DRAM的系统的增强的可靠性
- Patent Title: Implementing enhanced reliability of systems utilizing dual port DRAM
- Patent Title (中): 实现利用双端口DRAM的系统的增强的可靠性
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Application No.: US14227187Application Date: 2014-03-27
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Publication No.: US09251054B2Publication Date: 2016-02-02
- Inventor: Edgar R. Cordero , Carlos A. Fernandez , Joab D. Henderson , Jeffrey A. Sabrowski , Anuwat Saetow , Saravanan Sethuraman
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Joan Pennington
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F12/02 ; G06F11/10

Abstract:
A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.
Public/Granted literature
- US20150278086A1 IMPLEMENTING ENHANCED RELIABILITY OF SYSTEMS UTILIZING DUAL PORT DRAM Public/Granted day:2015-10-01
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